Positive response to Changxin 4F2 breakthrough, Micron CTO: 3D DRAM is "long-term more scalable and cost-effective"

The reason Changxin’s 4F² technology has drawn such intense industry attention is that it directly addresses the core commercial challenge of DRAM chips—bit density per wafer and cost.

In traditional DRAM design, the industry mainstream relies on the 6F² architecture. If a transition to 4F² succeeds, it is theoretically possible to shrink the cell size by more than 30% at the same process node, significantly increasing the number of effective dies (chip units) produced per wafer.

UBS’s follow-up on Micron’s technical communications revealed the company’s given production bottleneck analysis of 4F²:

First,the bottleneck lies in the capacitor, not the transistor. Micron believes that the ultimate bottleneck for DRAM scaling is capacitor pitch, rather than just the transistor cell structure. If capacitor spacing cannot be simultaneously compressed, merely switching to a 4F² structure will not directly translate to sustained cost advantages.

Second, the expansion ceiling for VCAT. The use of vertical channel transistors (VCAT) is typically required for 4F². According to Micron, apart from pitch compression, VCAT lacks a sustainable evolutionary path and introduces significant manufacturing complexities for processes such as ALD (Atomic Layer Deposition) and selective epitaxy, so the cost of volume production could erode the benefits of area shrinkage.

Deutsche Bank analyst Melissa Weathers summarized in her post-event report that Micron not only explicitly stated it does not plan to transition to the 4F² architecture, but also emphasized that it has internally evaluated and developed prototypes for the 4F² solution over several decades. The ultimate conclusion is: before the industry moves to 3D DRAM, 6F² remains the more attractive path.

Major Players Demonstrate Diverging Technical Considerations

UBS analysis points out that Micron’s statement essentially means it is progressing along two technical paths in parallel, similar to its hedged approach to EUV adoption at the 1-beta node. The company believes that 3D DRAM will eventually intersect with its roadmap and regards it as a “more scalable and cost-effective” long-term solution.

However, Micron’s logic does not represent an industry-wide consensus.

UBS’s research during the same period shows that, apart from Changxin’s intense efforts in this direction, industry leader Samsung is also rumored to be considering the introduction of 4F² at the future 0a nm node to alleviate process challenges related to high aspect ratio capacitors.

Samsung plans to complete volume production of 6F² at the 1d nm node in 2027 and aims to roll out 4F² at the 0a nm node before the end of 2028.

Beyond directly addressing doubts about 4F², Micron also highlighted its comprehensive technical layout at the webinar.

AI Memory Map Extension: Micron emphasized that AI’s demand for memory extends beyond single-layer HBM for training, and also includes LPDDR6, DDR6, SOCAMM, and 1TB large-capacity RDIMM for inference, edge AI, and autonomous driving scenarios.

Advanced Packaging and Logic Integration: Micron considers hybrid bonding as the core moat for 16-High and higher-spec HBM in the future, and is actively cooperating with foundries to develop vHBM (vertical stacking of memory atop compute cores). Micron is demonstrating that the competitive focus for storage in the AI era has shifted from “single-bit cost control” to “system-level synergy among memory, packaging, and logic architecture.”

NAND Value Reconfiguration: Micron also showcased its Gen11 NAND roadmap that exceeds 400 layers, emphasizing the drive to meet high-performance storage needs for high IOPS and bandwidth in the AI age and striving to build an integrated barrier between DRAM and NAND.