Intel’s Altera teams up with Riverlane on quantum error correction support for Agilex FPGAs

Reuters2026/09/10 15:00

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Intel’s Altera unit partnered with Riverlane to support real-time quantum error correction on Agilex FPGAs.
Riverlane validated its QEC Interface (QECi) design example on an Agilex 7 FPGA, targeting low-latency data movement.
Collaboration aims to help quantum hardware developers scale parallel processing, improve deterministic timing, reduce integration complexity.
Riverlane joined the Altera Solutions Acceleration Partner Program, expanding Altera’s partner ecosystem for FPGA-based quantum control systems.

Disclaimer: This news brief was created by Public Technologies (PUBT) using generative artificial intelligence. While PUBT strives to provide accurate and timely information, this AI-generated content is for informational purposes only and should not be interpreted as financial, investment, or legal advice. Intel Corporation published the original content used to generate this news brief via Business Wire (Ref. ID: 202609101100BIZWIRE_USPR_____20260909_BW900082) on September 10, 2026, and is solely responsible for the information contained therein.

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Intel’s Altera teams up with Riverlane on quantum error correction support for Agilex FPGAs

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